1. Technical Field
The disclosure relates generally to the field of high speed serial buses, as well as bus enumeration and network management thereof. More particularly, in one exemplary aspect, the disclosure is directed to methods and apparatus for augmenting routing resources of a PCI/PCIe based network technology. Various aspects of the present disclosure are directed to efficient management of bus enumeration during bus configuration processes.
2. Description of Related Technology
Peripheral Component Interconnect Express (PCIe), is a high-speed serial computer expansion bus technology that has very high adoption rates by computer and consumer electronics manufacturers. In fact, PCIe has become the de facto standard for adding additional input/output (I/O) capability beyond the functionality offered by a computer system base chipset. For example, the Thunderbolt™ connectivity ecosystem, couples a PCIe link (for high-speed peripheral device access) with a DisplayPort™ link (for high-speed display data capabilities).
Conceptually, PCIe was based on the older PCI expansion bus technology developed in 1993. At that time, the goal of PCI was to provide a standard method of adding hardware units to a computer bus. Each hardware unit was connected to a shared parallel bus, using a mechanism to identify each hardware unit as a unique device of the shared bus. Each device was further logically subdivided into up to eight functions. Thus, originally the PCI bus could support several devices, each with several functions. With the advent of PCIe, the physically shared parallel bus was replaced with a peer-to-peer high-speed serial bus. By removing the shared parallel bus, PCIe enabled support for full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.
Even though the legacy PCI hardware architecture did not directly translate to PCIe hardware, PCIe prioritized software compatibility with the PCI software architecture. For reasons described in greater detail herein, this imperfect translation introduced certain hardware limitations which greatly complicated and/or prevented the implementation of certain desirable bus capabilities. For example, incipient research into improved technologies which incorporate PCIe (such as the aforementioned Thunderbolt application) encounter hard limitations for use scenarios which are reconfigured during operation (e.g., hot-swapping, hot-plugging, etc.)
Ideally, improved methods and apparatus are needed to support dynamic changes to network topologies for PCIe based architectures. More generally, various solutions are needed for augmenting existing schemes for bus numbering and/or device identification.